1. Technical Field of the Invention
The present invention relates to a low noise output buffer capable of operating at high speeds.
2. Description of Related Art
Noise in a power supply is one of the major concerns considered while designing high-speed digital and analog I/O circuits. One of the major sources of supply noise is the switching of output drivers. The faster the I/O, the more current it requires and that implies higher noise. This may cause functional failures on a chip. So, providing a check on noise has become a main concern considered while designing high-speed output drivers.
Further, as CMOS devices are scaled down into the deep sub-micron region, the operating frequency of an output driver is increased (e.g., to frequencies over 50 MHz), which is reflected in terms of a reduction in rise/fall times and pulse widths. High switching speed leads to a fast rate of change of current (di/dt). A Simultaneous Switching Noise (SSN) event is created when many output drivers connected to a single supply switch simultaneously in the presence of a chip-package interface power distribution parasitic. This SSN must be limited to within a maximum allowable noise level in order to guarantee normal functioning of the buffers and the devices connected to the same supply. Therefore, power and ground noise has to be controlled for reliable operation of logic devices. Some of the encountered problems with false operations due to SSN are false triggering, double clocking and/or missing clocked pulses. A typical chip-package interface is shown in FIG. 1.
Supply and ground bounce due to SSN can be expressed as:Vbounce=n*L*di/dt Where n is the number of buffers switching together, L is the cumulative inductance of the trace, bonding wire and metal rail interconnects and di/dt is the rate of change of current of an output driver flowing through the supply and ground pad. As the parameters n and L (due to limitations from packaging) are not within the designer's control, the only quantity that can be controlled is the current slew rate for controlling supply/ground noise.
Supply noise can be suppressed by reducing the rate of change of charging and discharging current at the load. The rate of change of charging/discharging can be monitored by controlling the signals connected to gate of an output driver (i.e., signals GN and GP in FIG. 3) and/or using appropriate sized output driver transistors. The sizes of output driver transistors, however, are fixed due to a requirement that the output impedance match with the characteristic impedance of the transmission line or output drive specification for driving the TTL/CMOS load. FIG. 2 shows an equivalent circuit of an output driver final stage (compare to FIG. 3 components 33, 34 and 35).
FIG. 3 shows a block diagram of conventional compensated CMOS output buffer. It comprises tri-state logic 30, active slew rate control 31, a compensation cell 32, output driver transistors 33 and 34 connected to the output pad of the integrated circuit and a load capacitor 35. The circuit provides for the output buffer being compensated for slew rate at the rising edge only.
Generally, a pre-driver is used for controlling the slope of the signal connected to the gate of the output driver by which the slew on the rising edge can be controlled. The slew on the falling edge can be controlled by sizing of output driver. But in the case of high speed buffers, the output current is quite high due to the low output impedance of the driver when the PAD is at VOH and VOL levels and falls abruptly when the input transitions between low and high. When the input makes a transition from logic low to high, current at the load starts rising first and then starts falling gradually as the output driver PMOS goes into its linear operation region. Also, voltage at the PAD starts rising and reaches the required VOH value, but there is an abrupt fall in the current due to a change in logic at the input (from high to low) of the buffer as shown in waveform 2 of FIG. 4. This steep fall of current from a high value to zero when PMOS goes off at the falling edge of the current creates noise due to the high value of the slew rate when many output buffers switch together.
Thus, a circuit providing slew rate limitation at the falling edge is required.
There is accordingly a need to control the slew rate at the falling edge of current of the CMOS output driver.
There is further a need to provide a low noise output buffer capable of operating at high speeds.